1. Field of the Invention
The present invention relates to multi-port memories.
2. State of the Art
Multi-port memory structures are known. Most multi-port memories are dual-port memories. Applications do arise, however, for memory structures having a larger number of ports. Since memory bandwidth increases with the number of ports, memory structures having a large number of ports most commonly occur in high performance computers.
However, as the number of ports increases even modestly, the performance of conventional multi-port memories suffers. Referring to FIG. 1, the conventional way to implement a multi-port memory is to add two additional bit lines and an additional word line, with two N channel transistors for each port. For an N-port memory structure (e.g., an N-port register file), the transistor count would then be 2.sup.N +4. The layout efficiency drops very rapidly as the number of ports increases. The size of the N channel transistors in the memory latch must also be increased to insure that if multiple ports are simultaneously enabled, the cell will not get flipped (i.e., have its contents inverted). This constraint becomes very difficult to meet if a requirement of the device is that all the read ports can simultaneously access the same word. The cell also slows down as more and more ports are added.
Clearly, a need exists for input memory structures that are more readily scalable.